Multichip modules and hybrid circuits are commonly used to obtain a compact circuit with a desired function. These types of circuits are an inexpensive alternative to forming the circuit on a custom designed, single silicon die using microfabrication techniques. In one known embodiment of a compact circuit formed using these multichip modules and hybrid circuits, bare semiconductor chips are mounted on a custom fabricated substrate which has been constructed so that the necessary interconnections between the chips to be mounted on the substrate already exist.
In general, these types of hard-wired interconnect substrates require a large initial financial investment to fabricate, and a relatively long time is required to develop a prototype.
To reduce the lead time requirements and cost to fabricate interconnect substrates, programmable interconnect substrates have been introduced, such as those described in U.S. Pat. Nos. 4,458,297; 4,467,400; 4,487,737; and 4,479,088, all to Herbert Stopper. These patents disclose a programmable substrate intended specifically for the attachment of bare dice in specific locations on one side only of the substrate. One such programmable substrate is shown in prior art FIG. 1.
In FIG. 1, a pattern of cells is created on the surface of interconnect substrate 10, each cell offering a uniform pattern of bonding pads 12 for connection to terminals of bare die. Four cells are shown in FIG. 1, where each cell comprises a quadrant within the dashed line portion of FIG. 1; however, the substrate 10 contains many more cells. A small die, such as die 14 or die 16, may only occupy a single cell, while a large die, such as die 18, would occupy a number of adjacent cells. Large die 18 is shown as transparent in order to show the bonding pads 12 located under die 18. Since there are many different die sizes, the cell size (or size of a combination of cells) will often be larger than the optimal size for a particular die intended to be mounted on substrate 10. In this situation, portions of the interconnect substrate 10 would be wasted. Further, a single die may require more bonding pads than are offered by a cell; thus additional cells must be sacrificed.
The bonding pad patterns in the above-referenced patents to Stopper only support bare dice attachment. If a user of Stopper's technology were not able to obtain all the necessary circuit components as bare dice, but could only obtain the necessary circuit components through a combination of packaged components and bare dice, the interconnect substrate of FIG. 1 could not be used, since there is no provision on the substrate to mount a packaged device.
The programmable substrates described in the above-referenced patents are passive, having no transistors to aid in the programming or testing of the substrate.
Further, in the above-referenced patents to Stopper, interconnect elements are programmably formed between patterned metallization layers internal to the substrate. A first metallization layer contains a large number of parallel, separate conducting tracks which are orthogonal to a large number of parallel, separate conducting tracks in a second metallization layer. The tracks in the first layer, prior to programming, are not electrically connected to any tracks in the second layer. To program the substrate, a high voltage is applied between two orthogonal tracks. The dielectric material separating the two orthogonal tracks at their point of overlap is very thin so that the high potential difference breaks down the dielectric and causes the orthogonal tracks to fuse together at that point.
Such programmable interconnect elements are commonly known as antifuses, since they are an open circuit prior to programming. While incorporating these antifuses in a substrate enables the substrate to be fully programmed by programming relatively few antifuse elements, these antifuse elements have the drawback of being highly capacitive when unprogrammed, since each of these antifuse elements separate the metal layers by only a thin insulation layer portion. Because many of these antifuse elements are usually located along each conducting track, the total parallel capacitance can degrade the performance of circuits utilizing these interconnect substrates in certain applications.
Thus, an interconnect substrate which can efficiently accommodate both bare dice and packaged devices, and which has low capacitance conductive tracks is needed.